1. Field of the Invention
The present invention generally relates to a hysteresis comparator circuit and, more particularly, to a hysteresis comparator circuit suitable for generating a triangle waveform signal used for a DC/DC converter by using a pulse width modulation (PWM) method and a waveform generating circuit using such a hysteresis comparator circuit.
2. Description of the Related Art
Japanese Laid-Open Utility Model Application No. 6-86083 discloses a conventional hysteresis comparator circuit which includes a hysteresis comparator having a first input terminal to which an input voltage signal is input and a second input terminal to which a first threshold voltage or a second threshold voltage smaller than the first threshold voltage is selectively input. The second input voltage is input to the second input terminal via a switching element when an output voltage of the comparator is at a predetermined level. The hysteresis comparator circuit has a circuit structure in which the second threshold voltage is given priority over the first threshold voltage to be input to the second input terminal.
FIG. 1 shows a circuit diagram of a conventional waveform generating circuit having the above-mentioned hysteresis comparator circuit. The hysteresis comparator circuit 10A shown in FIG. 1 provides a hysteresis characteristic to a reference voltage V.sub.M of a comparator CMP by changing a ratio of resistances R.sub.1 :R.sub.2 :R.sub.3 of the resistive elements R.sub.1, R.sub.2 and R.sub.3.
For example, if the ratio of resistances R.sub.1 :R.sub.2 :R.sub.3 is set to 3:1:2 and the reference voltage source V.sub.ref is set to 1.8 V.sub.dc, a current I.sub.1 flowing from the reference voltage source V.sub.ref is represented by the following equation. EQU I.sub.1 =V.sub.ref .times.t.sub.1 /{(R.sub.1 +R.sub.2 +R.sub.3).times.t}+V.sub.ref .times.t.sub.2 /{(R.sub.1 +R.sub.2).times.t}
where t.sub.1 is a period during which a transistor Tr.sub.1 shown in FIG. 1 is turned off; t.sub.2 is a period during which the transistor Tr.sub.1 is turned on; and t is a sum of the period t.sub.1 and the period t.sub.2 (t=t.sub.1 +t.sub.2).
Accordingly, when the transistor Tr.sub.1 is turned off, the reference voltage V.sub.M of the comparator CMP is represented as follows. EQU V.sub.M =V.sub.ref .times.(R.sub.2 +R.sub.3)/(R.sub.1 +R.sub.2 +R.sub.3)=1.8.times.3/6=0.9 V
On the other hand, when the transistor Tr.sub.1 is turned on, the reference voltage V.sub.M of the comparator CMP is represented as follows. EQU V.sub.M =V.sub.ref .times.R.sub.2 /(R.sub.1 +R.sub.2)=1.8.times.1/4=0.45 V
Accordingly, in this case, the hysteresis provided to the reference voltage V.sub.M is 0.45 (=0.9-0.45) V.
The above-mentioned conventional hysteresis comparator circuit 10A is combined with a constant current charging and discharging circuit 20A so as to form a waveform generating circuit. As shown in FIG. 1, the constant current charging and discharging circuit 20A comprises transistors Tr.sub.2 and Tr.sub.3 and a capacitor C.sub.1. An integrating circuit (not shown in the figure) may be substituted for the constant current charging and discharging circuit 20A.
In the above-mentioned conventional hysteresis comparator circuit 10A, the sum of the resistances of the resistive elements R.sub.1, R.sub.2 and R.sub.3 is set to about 1 M.OMEGA.. Accordingly, there is a problem in that the current I.sub.1 continues to flow through the resistive elements R.sub.1, R.sub.2 and R.sub.3.
In order to reduce the current I.sub.1 flowing through the resistive elements R.sub.1, R.sub.2 and R.sub.3, the resistances of the resistive elements R.sub.1, R.sub.2 and R.sub.3 must be set to large values. However, if the resistances of the resistive elements R.sub.1, R.sub.2 and R.sub.3 are increased, an impedance of the resistive circuit comprising the resistive elements R.sub.1, R.sub.2 and R.sub.3 is also increased. As a result, there is a problem in that the circuit is unstable with respect to a sharp voltage fluctuation of the power source.
The above-mentioned waveform generating circuit provided with the hysteresis comparator circuit 10A or a DC/DC converter provided with the waveform generating circuit is used for converting a level of a DC voltage. The conversion of the level of the DC voltage may include a voltage increasing conversion, a voltage decreasing conversion and a polarity reversing conversion. In such a conversion, a power conversion efficiency is an important factor. Especially, in a case in which a CPU is connected to a DC/DC converter and when the CPU is set in a sleep mode, the power conversion efficiency of the DC/DC converter is greatly influenced by the power consumed by the DC/DC converter itself. Thus, in such a case, there is a problem in that the power conversion efficiency is decreased.